1. Field of the Invention
This present invention is generally directed to the field of integrated circuits and semiconductor processing, and, more particularly, to a method of using high-k dielectric materials to reduce soft errors in static random access memory (SRAM) memory cells, and a device comprising same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. In general, modem, integrated circuit devices and applications mandate high-performance memory structures to aide in processing and storing the vast volume of data processed by such devices. Thus, as the integration density and processing power of various integrated circuit devices has increased, e.g., application-specific circuits, microprocessors, etc., efforts have been made to increase the density and operating speed of such memory structures.
Relatively speaking, an SRAM memory cell provides a very fast read access speed. Accordingly, SRAM cells are widely used in integrated circuits. An SRAM cell is considered to be a bi-stable circuit because it has two stable or self-maintaining operating states that correspond to two different output voltages, or logic states. Typically, the different voltages correspond to a binary stored xe2x80x9c1xe2x80x9d (logically high) or xe2x80x9c0xe2x80x9d (logically low). Without external stimuli, an SRAM memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable voltage differential between two nodes of the cell. The polarity of this voltage difference is sensed by external circuitry to determine the operating state of the SRAM cell. The two possible output voltages produced by an SRAM cell are typically determined by the upper and lower circuit supply voltages.
FIG. 1 is a cross-sectional view of a portion of an illustrative SRAM cell 10 formed above a semiconducting substrate 12, such as silicon. The SRAM cell 10 is generally comprised of two transistors 16, each of which is comprised of a gate insulation layer 17, a gate electrode 19, a protective cap layer 21, and a plurality of source/drain regions 15. The transistors 16 are formed between isolation structures 14 formed in the substrate 12. Typically, a plurality of local interconnects 13 are formed in a BPSG (boron phosphosilicate glass) layer 11. The BPSG layer 11 may be formed by a variety of deposition techniques, e.g., chemical vapor deposition (xe2x80x9cCVDxe2x80x9d), plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d), etc. The thickness of the BPSG layer 11 may vary depending upon the device under construction. Typically, the BPSG layer 11 may have a thickness that ranges from approximately 500-1000 nm (5000-10000 xc3x85). More importantly, in traditional SRAM cells, the local interconnects 13 are positioned within the insulating BPSG layer 11. Typically, the BPSG layer 11 will be deposited and a plurality of openings 25 will be formed therein by performing known photolithography and etching techniques. Thereafter, the local intcrconnects 13 will be formed in the openings 25 in the BPSG layer 11.
Alpha particles are naturally occurring ionizing radiation which can penetrate into the silicon substrate of the SRAM cell 10 depicted in FIG. 1 and generate electron-hole pairs. One source of alpha particles is the decay of radioactive impurities such as uranium or thorium, known to be present in trace levels in common semiconductor packaging materials. The alpha particles, from whatever source, can generate sufficient charge adjacent an SRAM memory cell node to upset the data state of the SRAM memory cell, i.e., it can cause the SRAM cell 10 to flip from a xe2x80x9c1xe2x80x9d to a xe2x80x9c0,xe2x80x9d or vice versa. Such events are termed xe2x80x9csoft errorsxe2x80x9d in the industry. Soft error rates must be controlled to very low levels for reliable operation of semiconductor devices.
Typically, the boron element used in the BPSG layer 11 is B10, which has a relatively large capture cross-section. As a result, the alpha particles striking the BPSG layer 11 (comprised of B10) tend to split and enter the silicon with the tendency to thereby cause soft errors. To counteract this problem, efforts have been made to replace the BPSG layer 11 with phosphosilicate glass (PSG), i.e., to eliminate the use of B10, or to replace the B10 material with B11, a version of boron that has a smaller capture cross-section. Despite these efforts, soft errors in SRAM memory cells continue to be a problem that must be addressed. This is particularly important for integrated circuit devices intended for use in space applications or satellite communications.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of using high-k dielectric materials to reduce soft errors in SRAM devices, and a device comprising same. In one illustrative embodiment, the method comprises forming a plurality of transistors above a semiconducting substrate, forming a layer comprised of boron phosphosilicate glass (BPSG) above the substrate and the transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect (LI) in each of the openings.
In another illustrative embodiment, the method comprises forming a plurality of transistors above a semiconducting substrate, forming a layer comprised of boron phosphosilicate glass (BPSG) above the substrate and between the transistors, forming a plurality of openings in the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, forming a conductive local interconnect in each of the openings, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects.
In yet another illustrative embodiment, a memory cell is provided that comprises a plurality of transistors formed above a semiconducting substrate and a plurality of local interconnects, each of which is conductively coupled to a doped region, i.e., a source/drain region, of one of the transistors. The local interconnects are positioned in openings in a layer of boron phosphosilicate glass (BPSG) and a dielectric layer positioned above the BPSG layer, the dielectric layer being comprised of a material having a dielectric constant greater than approximately 6.0.